STT-RAM Aware Last-Level-Cache Policies for Simultaneous Energy and Performance Improvement

High capacity Last Level Cache (LLC) architectures have been proposed to mitigate the widening processor-memory speed gap. These LLC architectures have been realized using DRAM or SpinTransfer-Torque Random Access Memory (STT-RAM) memory technologies. It has been shown that STT-RAM LLC provides improved energy efficiency compared to DRAM LLC. However, existing STT-RAM LLC suffers from increased energy consumption by fetching unncesseary cache lines into the row buffer. To address this problem, we propose a Selective Read Policy for STT-RAM LLC. This policy is based on the idea of fetching those cache lines into the row buffer that are likely to be reused. This policy restricts the number of unneeded cache line reads and thereby reduces the energy consumption. While the Selective Read Policy provides energy reduction, it introduces a latency penalty. To address this problem, we propose three performance optimizations namely Row Buffer Tags Bypass Policy, LLC Data Cache, and a Tag Organization. These optimizations reduce the impact of the latency penalty of Selective Read Policy while considering STT-RAM and application characteristics. For an 8-core system, we show that our synergetic policies reduce the average LLC dynamic energy consumption by 72.6% and improve the system performance by 1.3% compared to the recently proposed STT-RAM LLC. Compared to the state-of-the-art DRAM LLC, our architecture reduces the LLC dynamic energy consumption by 90.6% and improves the system performance by 1.4%.